1. Field of the Invention
The present invention relates to a system on chip (SOC), and more particularly to a SOC with cores and a method of testing and debugging the same.
2. Description of Related Art
Generally, the SOC includes a plurality of cores in a single chip. The cores embedded in the SOC are separately designed and tested before being combined in a chip. However, even if each core is normally operated when it is tested separately, when the cores are combined in a chip, they may not operate properly.
A plurality of cores embedded in a single chip may be tested in accordance with the IEEE standard 1149.1. According to IEEE standard 1149.1, three or four test input pins and one test output pin (TDO) may be used for testing and debugging the cores in the SOC. The three or four test input pins include a test data input pin (TDI), a test clock signal input pin (TCK), a test mode signal input pin (TMS) and a test reset signal input pin (which is optional). The test output pin (TDO) is used for outputting test data. The test clock signal input pin (TCK) and test mode signal (TMS) are input to a tap controller and the test data input (TDI) is input to an instruction register. The test output pin (TDO) is output by an output multiplexer.
The cores are placed in a test mode upon application of a test mode signal applied through the test mode signal input pin (TMS). The cores are reset by a reset signal applied through the test reset signal input pin and output the test data in response to a test clock signal input from the test clock signal input pin (TCK). The test data are input and output through the test data input pin (TDI) and test data output pin (TDO), respectively.
It may be desirable for an SOC having a plurality of cores to be tested and debugged in accordance with the IEEE standard 1149.1. However, the IEEE standard 1149.1 only provides a method of testing each core embedded in the SOC separately.
FIG. 1 is a block diagram of an SOC with cores according to IEEE standard 1149. 1 in accordance with one example of the conventional art. The conventional SOC 100 includes a chip level circuit 10, a first core 20 and a second core 30.
The chip level circuit 10 includes boundary scan registers 12-1 and 12-2, a test access port (TAP) controller 14 and a chip level logic circuit 16. The first core 20 includes boundary scan registers 22-1 and 22-2, a TAP controller 24 and a first logic circuit 26. The second core 30 includes boundary scan registers 32-1 and 32-2, a TAP controller 34 and a second logic circuit 36.
The SOC 100 includes test pins TDI, TMS, TRST, TCK and TDO for testing and debugging the chip level circuit 10, TDIA, TMSA, TRSTA, TCKA and TDOA for the first core 20, and TDIB, TMSB, TRSTB, TCKB and TDOB for the second core 30.
As shown in FIG. 1, all of the test pins are provided for every core 20, 30 and the chip level circuit 10. Accordingly, the number of the test pins of the SOC 100 increases as the number of the cores or chip level circuits embedded in the chip increases.
FIG. 2 is a block diagram showing a SOC 200 with cores according to IEEE standard 1149.1 in accordance with another example of the conventional art. The SOC 200 shown in FIG. 2 includes a chip level circuit 10, a first core 20, a second core 30 and a multiplexer 40. A detailed circuit configuration of the chip level circuit 10, the first core 20 and the second core 30 in FIG. 2 may be the same as in FIG. 1. The SOC 200 has a set of test pins TDI, TMS, TRST, TCK and TDO commonly used for testing each circuit block such as the chip level circuit 10, the first core 20 and the second core 30 and two selection signal pins SEL1 and SEL2 for receiving selection signals for controlling the multiplexer 40.
When the selection signals “00” are applied to the SOC 200 through the selection pins SEL1 and SEL2, the chip level circuit 10 is tested and debugged using the set of test pins TDI, TMS, TRST, TCK and TDO. When the selection signals “01” are applied to the SOC 200 through the selection pins SEL1 and SEL2, the first core 20 is tested and debugged using the set of test pins TDI, TMS, TRST, TCK and TDO. When the selection signals “10” are applied to the SOC 200 through the selection pins SEL1 and SEL2, the second core 30 is tested and debugged using the set of test pins TDI, TMS, TRST, TCK and TDO.
The SOC 200 in FIG. 2 has an advantage of having reduced test pins in comparison with the SOC 100 in FIG. 1. However, relative operation, operational interaction, and operational interference between the cores 20, 30 and the chip level circuit 10 and a general operation of the SOC 200 are not tested in either conventional example.